Altera University Program Video IP Cores - FTP - For Quartus II 11.0 1 Overview Video IP Cores for Altera DE-Series Boards The Altera University Program (UP) Video IP cores facilitate decoding, processing and display of video data. Brendel br 301 manualidades. They are designed for use on Altera DE-series boards and work with on-board video-in and VGA chips, as well as Terasic’s 5 megapixel CCD camera and LCD screen with touch panel daughtercards. This suite of IP cores comprises: a video decoder, a VGA controller, eleven video-processing cores, two direct-memory-access (DMA) cores, a character buffer and two Video Image Processing (V IP) bridges. The video decoder converts raw video input from videoin chips on Altera DE2/DE2-70/DE2-115 boards, or Terasic’s 5 megapixel CCD camera, into packets that can be processed by the video-processing cores. The VGA controller core displays images by creating the timing signals required by VGA compatible monitors attached to the VGA port on the DE-series board, or the Terasic LCD screen with touch panel. The video-processing cores perform basic transformations on the video input, while the V IP bridge cores allow Altera V IP cores to be used together with Altera UP Video IP cores in more advanced applications. The video DMA cores allow video data to be stored to and retrieved from memory. The character buffer core holds ASCII characters and converts them to a video stream, so that they can be displayed on a screen. The remainder of this manual is organized as follows: Section 2 gives a brief introduction of the cores and gives four examples to assist designers using the video IP cores. Section 3, named Background, describes in detail how the video IP core are connected, the format used to transfer data and the memory layout for stored video. A detailed description of all the UP video cores is given in Section 4. This manual assumes that the reader is familiar with the Altera SOPC Builder tool and how to use it. 2 Getting Started In this section, the cores will be briefly described through the use of four examples. file that implements this system, as well as its design source files, can be obtained from the University Program section of Altera’s web site. Design ContestsThe examples use the VGA output and video input ports on the DE-series boards. All examples were created using SOPC Builder, and include a Nios II processor and a 16 KB on-chip memory as a base system. All of these examples are available in the IP cores directory, which is installed using the University Program Design Suite package. Materials2.1 Basic Video Out: Character Display The first example demonstrates how to display characters on a VGA-compatible screen that is attached to the VGA port on the DE-series board. In this example, we make use of the following four cores: the VGA controller, Clock Signals, Dual-Clock FIFO and Character Buffer for VGA Display. Altera Corporation - University Program May 2011 1.
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